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FEATURES Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB Effective Number of Bits: 9.5 Signal-to-Noise and Distortion Ratio: 59 dB Spurious-Free Dynamic Range: 71 dB 2 Interpolation Filters 20 MSPS/Channel Data Rate Single Supply: +2.7 V to +5.5 V Low Power Dissipation: 200 mW (+3 V Supply @ 40 MSPS) On-Chip Reference 28-Lead SSOP PRODUCT DESCRIPTION
Dual 10-Bit TxDAC+TM with 2 Interpolation Filters AD9761
FUNCTIONAL BLOCK DIAGRAM
DCOM DVDD CLOCK ACOM AVDD IOUTA IOUTB REFLO FSADJ REFIO COMP1 COMP2 COMP3 QOUTA QOUTB LATCH "I" "I" DAC
2
SLEEP
REFERENCE DAC DATA INPUTS (10 BITS)
BIAS GENERATOR LATCH "Q" "Q" DAC
2
WRITE INPUT SELECT INPUT
MUX CONTROL
AD9761
The AD9761 is a complete dual channel, high speed, 10-bit CMOS DAC. The AD9761 has been developed specifically for use in wide bandwidth communication applications (e.g., spread spectrum) where digital I and Q information is being processed during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2x interpolation filters, a voltage reference, and digital input interface circuitry. The AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2x up to 40 MSPS before simultaneously updating each DAC. The interleaved I and Q input data stream is presented to the digital interface circuitry, which consists of I and Q latches as well as some additional control logic. The data is de-interleaved back into its original I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. The data output from each latch is then processed by a 2x digital interpolation filter that eases the reconstruction filter requirements. The interpolated output of each filter serves as the input of their respective 10-bit DAC. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output thus supporting single-ended or differential applications. Both DACs are simultaneously updated and provide a nominal full-scale current of 10 mA. Also, the full-scale currents between each DAC are matched to within 0.07 dB (i.e., 0.75%), thus eliminating the need for additional gain calibration circuitry. The AD9761 is manufactured on an advanced low cost CMOS process. It operates from a single supply of 2.7 V to 5.5 V and consumes 200 mW of power. To make the AD9761 complete it also offers an internal 1.20 V temperature-compensated bandgap reference.
TxDAC+ is a trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTS
1. Dual 10-Bit, 40 MSPS DACs: A pair of high performance 40 MSPS DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 2. 2x Digital Interpolation Filters: Dual matching FIR interpolation filters with 62.5 dB stop band rejection precede each DAC input thus reducing the DACs' reconstruction filter requirements. 3. Low Power: Complete CMOS Dual DAC function operates on a low 200 mW on a single supply from 2.7 V to 5.5 V. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for power reduction during idle periods. 4. On-Chip Voltage Reference: The AD9761 includes a 1.20 V temperature-compensated bandgap voltage reference. 5. Single 10-Bit Digital Input Bus: The AD9761 features a flexible digital interface allowing each DAC to be addressed in a variety of ways including different update rates. 6. Small Package: The AD9761 offers the complete integrated function in a compact 28-lead SSOP package. 7. Product Family: The AD9761 Dual Transmit DAC has a pair of Dual Receive ADC companion products, the AD9281 (8 bits) and AD9201 (10 bits).
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 7817/326-8703 (c) Analog Devices, Inc., 2000
AD9761-SPECIFICATIONS
DC SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) TA = +25C TMIN to TMAX Differential Nonlinearity (DNL) TA = +25C TMIN to TMAX Monotonicity (10 Bit) ANALOG OUTPUT Offset Error Offset Matching between DACs Gain Error (without Internal Reference) Gain Error (with Internal Reference) Gain Matching between DACs Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (without Internal Reference) Gain Drift (with Internal Reference) Gain Matching Drift (Between DACs) Reference Voltage Drift POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD ) DVDD Voltage Range Digital Supply Current at 5 V (IDVDD)4 Digital Supply Current at 3 V (IDVDD)4 Nominal Power Dissipation5 AVDD and DVDD at 3 V AVDD and DVDD at 5 V Power Supply Rejection Ratio (PSRR)-AVDD Power Supply Rejection Ratio (PSRR)-DVDD OPERATING RANGE
1
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, unless otherwise noted)
Min 10 Typ Max Units Bits
-1.75 -2.75
0.5 0.7
1.75 2.75
LSB LSB
-1 0.4 1.25 LSB -1 0.5 1.75 LSB GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE -0.05 -0.10 -5.5 -5.5 -1.0 -1.0 100 5 1.14 1.20 100 1.26 0.025 0.05 1.0 1.0 0.25 10 0.05 0.10 5.5 5.5 1.0 1.25 % of FSR % of FSR % of FSR % of FSR % of FSR mA V k pF V nA V M ppm/C ppm/C ppm/C ppm/C ppm/C
0.1 1 0 50 140 25 50
1.25
2.7
5.0 26 5.0 70 35 200 500
5.5 35 5.5 85
V mA V mA mA mW mW % of FSR/V % of FSR/V C
2.7
-0.25 -0.02 -40
250 650 0.25 0.02 +85
NOTES 1 Measured at IOUTA and QOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS , is 16x the I REF current. 3 Use an external amplifier to drive any external load. 4 Measured at fCLOCK = 40 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output into 50 RLOAD at IOUTA, IOUTB, QOUTA, and QOUTB, f CLOCK = 40 MSPS and f OUT = 8 MHz. Specifications subject to change without notice.
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REV. A
AD9761 DYNAMIC SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate Output Settling Time (tST to 0.025%) Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion (SINAD) fOUT = 1 MHz; CLOCK = 40 MSPS Effective Number of Bits (ENOBs) Total Harmonic Distortion (THD) fOUT = 1 MHz; CLOCK = 40 MSPS Spurious-Free Dynamic Range (SFDR) fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span Channel Isolation fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted)
Min 40 35 55 5 2.5 2.5 Typ Max Units MSPS ns Input Clock Cycles pV-s ns ns
56 9.0
59 9.5 -68 -58
dB Bits dB dB dBC
59
68 90
DIGITAL SPECIFICATIONS (T
Parameter
MIN
to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA unless otherwise noted)
Min 3.5 2.4 Typ 5 3 0 0 Max Units V V V V A A pF ns ns ns ns ns
DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" Voltage @ DVDD = +3 V Logic "0" Voltage @ DVDD = +5 V Logic "0" Voltage @ DVDD = +3 V Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) CLOCK High CLOCK Low Invalid CLOCK/WRITE Window (tCINV)1
-10 -10 5 3 2 5 5 1
1.3 0.9 +10 +10
5
NOTES 1 tCINV is an invalid window of 4 ns duration beginning 1 ns AFTER the rising edge of WRITE in which the rising edge of CLOCK MUST NOT occur. Specifications subject to change without notice.
tS
DB9-DB0 DAC INPUTS
tH
"I" DATA
"Q" DATA
SELECT
WRITE
NOTES: WRITE AND CLOCK CAN BE TIED TOGETHER. FOR TYPICAL EXAMPLES, REFER TO DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATION SECTION.
CLOCK
tCINV
Figure 1. Timing Diagram
REV. A
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AD9761 DIGITAL FILTER SPECIFICATIONS otherwise noted)
Parameter MAXIMUM INPUT CLOCK RATE (fCLOCK) DIGITAL FILTER CHARACTERISTICS Passband Width1: 0.005 dB Passband Width: 0.01 dB Passband Width: 0.1 dB Passband Width: -3 dB Linear Phase (FIR Implementation) Stopband Rejection: 0.3 fCLOCK to 0.7 fCLOCK Group Delay2 Impulse Response Duration3 -40 dB -60 dB Min 40 0.2010 0.2025 0.2105 0.239 -62.5 32 28 40
(TMIN to TMAX, AVDD = +2.7 V to 5.5 V, DVDD = +2.7 V to 5.5 V, IOUTFS = 10 mA unless
Typ Max Units MSPS fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK dB Input Clock Cycles Input Clock Cycles Input Clock Cycles
NOTES 1 Excludes SINX/X characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. 3 55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
0
Table I. Integer Filter Coefficients for 43-Tap Halfband FIR Filter
-20
Lower Coefficient
OUTPUT - dBFS -40
Upper Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23)
Integer Value 1 0 -3 0 8 0 -16 0 29 0 -50 0 81 0 -131 0 216 0 -400 0 1264 1998
-60
-80
-100
-120
0
0.1 0.2 0.3 0.4 FREQUENCY RESPONSE - DC to fCLOCK/2
0.5
Figure 2a. FIR Filter Frequency Response
1 0.9 0.8 0.7 NORMALIZED OUTPUT 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 5 10 15 20 25 TIME - Samples 30 35 40
H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22)
Figure 2b. FIR Filter Impulse Response
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REV. A
AD9761
ORDERING GUIDE
Model
Package Description
Package Option
THERMAL CHARACTERISTICS Thermal Resistance
28-Lead SSOP JA = 109C/W
AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761-EB Evaluation Board
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD DVDD ACOM AVDD CLOCK, WRITE SELECT, SLEEP Digital Inputs IOUTA, IOUTB QOUTA, QOUTB COMP1, COMP2 COMP3 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect to ACOM DCOM DCOM DVDD DCOM DCOM DCOM ACOM ACOM ACOM ACOM ACOM ACOM
Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -1.0 -1.0 -0.3 -0.3 -0.3 -0.3 -65
Max +6.5 +6.5 +0.3 +6.5 DVDD+0.3 DVDD+0.3 DVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 +0.3 +150 +150 +300
Units V V V V V V V V V V V V V C C C
*This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
+2.7V TO 5.5V
+2.7V TO 5.5V
0.1 F DVDD DCOM COMP3 LATCH "I" AVDD
0.1 F AVSS COMP1 "I" DAC
0.1 F MINI-CIRCUITS T1-1T 100 TO HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 50 20pF
COMP2 IOUTA IOUTB REFLO
2x
TEKTRONIX AWG-2021
DIGITAL DATA DB9-DB0
50
20pF
AD9761
REFIO FSADJ 0.1 F RSET 2k
MINI-CIRCUITS T1-1T 100 TO HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 50 20pF
CLOCK OUT MARKER 1 SELECT WRITE RETIMED CLOCK OUTPUT* CLOCK
LATCH "Q" MUX CONTROL
2x
"Q" DAC
QOUTA QOUTB
50 SLEEP
20pF
*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA
LE CROY 9210 PULSE GENERATOR TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
Figure 3. Basic AC Characterization Test Setup
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9761 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
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AD9761
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2-9 10 11 12 13 14 15 16 17 18 19 20
Name DB9 DB8-DB1 DB0 CLOCK WRITE SELECT DVDD DCOM COMP3 QOUTA QOUTB REFLO REFIO
Description Most Significant Data Bit (MSB). Data Bits 1-8. Least Significant Data Bit (LSB). Clock Input. Both DACs' outputs updated on positive edge of clock and digital filters read respective input registers. Write input. DAC input registers latched on positive edge of write. Select Input. Select high routes input data to I DAC, select low routes data to Q DAC. Digital Supply Voltage (+2.7 V to +5.5 V). Digital Common. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor. Q DAC Current Output. Full-scale current when all data bits are 1s. Q DAC Complementary Current Output. Full-scale current when all data bits are 0s. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V reference output when internal reference activated. Requires 0.1 F capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current. Bandwidth/Noise Reduction Node. Add 0.1 F to AVDD for optimum performance. Analog Supply Voltage (+2.7 V to +5.5 V). Analog Common. I DAC Complementary Current Output. Full-scale current when all data bits are 0s. I DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 F capacitor. Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP section.
21 22 23 24 25 26 27 28
FSADJ COMP2 AVDD ACOM IOUTB IOUTA COMP1 RESET/SLEEP
PIN CONFIGURATION
(MSB) DB9 1 DB8 2 DB7 3 DB6 4 DB5 5 DB4 6 28 RESET/SLEEP 27 COMP1 26 IOUTA 25 IOUTB
AD9761
24 ACOM
TOP VIEW 23 AVDD DB3 7 (Not to Scale) 22 COMP2 DB2 8 DB1 9 (LSB) DB0 10 CLOCK 11 WRITE 12 SELECT 13 DVDD 14 21 FSADJ 20 REFIO 19 REFLO 18 QOUTB 17 QOUTA 16 COMP3 15 DCOM
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AD9761
DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Channel Isolation
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
Channel Isolation is a measure of the level of crosstalk between channels. It is measured by producing a full-scale 8 MHz signal output for one channel and measuring the leakage into the other channel.
Spurious-Free Dynamic Range
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
THD is the ratio of the sum of the rms value of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
S/N+D is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD - 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Passband
The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the ambient (+25C) value to the value at either TMIN or TMAX . For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C.
Power Supply Rejection
Frequency band in which any input applied therein passes unattenuated to the DAC output.
Stopband Rejection
The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
Settling Time
The amount of attenuation of a frequency outside the passband applied to the DAC, relative to a full-scale signal applied at the DAC input within the passband.
Group Delay
Number of input clocks between an impulse applied at the device input and peak DAC output current.
Impulse Response
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Glitch Impulse
Response of the device to an impulse applied to the input.
Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified the net area of the glitch in pV-s.
REV. A
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AD9761 Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, 50 performance shown)
0 -10 -20 10dB - Div -30 -40 ENOB dB -50 -60 -70 -80 S/E -6dBFS -90 -100 50 START: 0Hz STOP: 40MHz 0 2.0 4.0 6.0 fOUT - MHz 8.0 8.01 10.0 65 0 DIFF 0dBFS 5.0 fOUT - MHz 10.0 55 DIFF -6dBFS 8.84 70 S/E 0dBFS dB S/E -6dBFS S/E 0dBFS DIFF -6dBFS 60 DIFF 0dBFS 9.67 75
Doubly Terminated Load, TA = +25 C, fCLOCK = 40 MSPS, unless otherwise noted, worst of I or Q output
65
10.5
80
Figure 4. Single-Tone SFDR (DC to 2 fDATA, f CLOCK = 2 fDATA)
Figure 5. SINAD (ENOBs) vs. fOUT (DC to fDATA/2)
Figure 6. SFDR vs. f OUT (DC to f DATA/2)
75
80 75
SFDR @ 40MSPS SFDR @ 20MSPS SFDR @ 10MSPS dB
80 SFDR @ 40MSPS 75 70 65 SFDR @ 10MSPS 60 55 50 SFDR @ 20MSPS
70 DIFF -6dBFS
70 65
65 dB dB S/E 0dBFS 55 S/E -6dBFS 50 0 2.0 4.0 6.0 8.0 10.0 fOUT - MHz 45 40 35 -30 -25 -20 -15 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS -10 -5 -0 45 40 35 -30 -25 -20 -15 DIFF 0dBFS 60 60 55 50
SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS -10 -5 0
AOUT - dBFS
AOUT - dBFS
Figure 7. "Out-of-Band" SFDR vs. f OUT (fDATA/2 to 3/2 fDATA)
Figure 8. SINAD vs. AOUT (DC to fDATA/2, Differential Output)
Figure 9. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output)
80 SFDR @ 2.5mA 75
80 SFDR @ 5mA 75 SFDR @ 10mA 10dB - Div
-45 -55 -65 -75 -85 -95 SINAD @ 10mA -105
70 dB
SFDR @ 10mA dB SFDR @ 5mA
70 SFDR @ 2.5mA 65 SINAD @ 5mA SINAD @ 2.5mA 60
65
SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA
60
55 0
55 2 4 6 fOUT - MHz 8 10 0
2
4 6 fOUT - MHz
8
10
START: 0Hz
STOP: 20MHz
Figure 10. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Differential Output)
Figure 11. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Single-Ended Output)
Figure 12. Wideband SpreadSpectrum Spectral Plot (DC to fDATA)
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REV. A
AD9761 Typical AC Characterization Curves @ +3 V Supplies
(AVDD = +3 V, DVDD = +3 V, 50 performance shown)
0 -10 -20 10dB - Div -30 dB -40 -50 -60 -70 -80 -90 50 START: 0Hz STOP: 10MHz 0 0.5 1.0 1.5 fOUT - MHz 2.0 8.01 2.5 60 0 0.5 1.0 1.5 fOUT - MHz 2.0 2.5 55 DIFF -6dBFS S/E -6dBFS 8.84 DIFF 0dBFS 65 S/E 0dBFS 60 DIFF 0dBFS S/E 0dBFS 9.67 75 ENOB dB 80 S/E -6dBFS
Doubly Terminated Load, TA = +25 C, fCLOCK = 10 MSPS, unless otherwise noted, worst of I or Q output
65
10.5
85 DIFF -6dBFS
70
Figure 13. Single-Tone SFDR (DC to 2 fDATA, f CLOCK = 2 fDATA)
Figure 14. SINAD (ENOBs) vs. fOUT (DC to fDATA/2)
Figure 15. SFDR vs. fOUT (DC to fDATA/2)
80 DIFF -6dBFS 75 S/E 0dBFS
80 75
SFDR @ 20MSPS SFDR @ 10MSPS
75 70 65 60
SFDR @ 20MSPS SFDR @ 10MSPS
70 65 SFDR @ 40MSPS
SFDR @ 40MSPS
dB
dB
70 DIFF 0dBFS 65
S/E -6dBFS
dB
60 55 50 45 40 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS -25 -20 -15 -10 AOUT - dBFS -5 0
55 50 45 40 35 30 -30 -25 -20 -15 -10 AOUT - dBFS -5 0 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS
60 0 0.5 1.0 1.5 fOUT - MHz 2.0 2.5
35 -30
Figure 16. "Out-of-Band" SFDR vs. fOUT (f DATA/2 to 3/2fDATA)
Figure 17. SINAD vs. AOUT (DC to fDATA/2, Differential Output)
Figure 18. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output)
80 SFDR @ 10mA
80 SFDR @ 5mA
0 -10 -20 10dB - Div SINAD @ 5mA SINAD @ 10mA 8 10 -30 -40 -50 -60 -70
75
75 SFDR @ 10mA
70 dB SFDR @ 5mA 65
SFDR @ 2.5mA dB
70 SFDR @ 2.5mA 65
60
SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA
SINAD @ 2.5mA 60
55 0
2
4 6 fOUT - MHz
8
10
55
0
2
4 6 fOUT - MHz
-80 START: 0Hz STOP: 10MHz
Figure 19. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Differential Output)
Figure 20. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Single-Ended Output)
Figure 21. Narrowband SpreadSpectrum Spectral Plot (DC to f DATA)
REV. A
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AD9761
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9761. The AD9761 is a complete dual channel, high speed, 10-bit CMOS DAC capable of operating up to a 40 MHz clock rate. It has been optimized for the transmit section of wideband communication systems employing I and Q modulation schemes. Excellent matching characteristics between channels reduces the need for any external calibration circuitry. Dual matching 2x interpolation filters included in the I and Q data path simplify any post, bandlimiting filter requirements. The AD9761 interfaces with a single 10-bit digital input bus that supports interleaved I and Q input data.
DCOM DVDD CLOCK ACOM AVDD IOUTA IOUTB REFLO FSADJ REFIO COMP1 COMP2 COMP3 QOUTA QOUTB
four most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The full-scale output current, IOUTFS, of each DAC is regulated from the same voltage reference and control amplifier, thus ensuring excellent gain matching and drift characteristics between DACs. IOUTFS can be set from 1 mA to 10 mA via an external resistor, RSET . The external resistor in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IREF, which is mirrored over to the segmented current sources with the proper scaling factor. IOUTFS is exactly sixteen times the value of IREF. The I and Q DACs are simultaneously updated on the rising edge of CLOCK with digital data from their respective 2x digital interpolation filters. The 2x interpolation filters essentially multiplies the input data rate of each DAC by a factor of two, relative to its original input data rate while simultaneously reducing the magnitude of first image associated with the DAC's original input data rate. Since the AD9761 supports a single 10-bit digital bus with interleaved I and Q input data, the original I and Q input data rate before interpolation is one-half the CLOCK rate. After interpolation, the data rate into each I and Q DAC becomes equal to the CLOCK rate. The benefits of an interpolation filter are clearly seen in Figure 23, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to a digital interpolation filter. Images of the sine wave signal appear around multiples of the DAC's input data rate as predicted by the sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although modified by the DAC's sin(x)/(x) response. In many bandlimited applications, these images must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression.
SLEEP
LATCH "I"
2
"I" DAC
REFERENCE DAC DATA INPUTS (10 BITS)
BIAS GENERATOR LATCH "Q" "Q" DAC
2
WRITE INPUT SELECT INPUT
MUX CONTROL
AD9761
Figure 22. Dual DAC Functional Block Diagram
Referring to Figure 22, the AD9761 consists of an analog section and a digital section. The analog section includes matched I and Q 10-bit DACs, a 1.20 V bandgap voltage reference and a reference control amplifier. The digital section includes: two 2x interpolation filters; segment decoding logic; and some additional digital input interface circuitry. The analog and digital sections of the AD9761 have separate power supply inputs (i.e., AVDD and DVDD) that can operate over a 2.7 V to 5.5 V range. Each DAC consists of a large PMOS current source array capable of providing up to 10 mA of full-scale current, IOUTFS. Each array is divided into 15 equal currents that make up the
TIME DOMAIN 2 1
fCLOCK
FUNDAMENTAL 1ST IMAGE
fCLOCK
FUNDAMENTAL DIGITAL FILTER DACs "NEW" 1ST IMAGE "SINX" X
FREQUENCY DOMAIN
fCLOCK
2
fCLOCK
SUPPRESSED "OLD" 1ST IMAGE
fCLOCK
2
fCLOCK
fCLOCK
2
fCLOCK
INPUT DATA LATCH
2x INTERPOLATION FILTER
DAC
2x
fCLOCK
2
fCLOCK
Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter
-10-
REV. A
AD9761
Referring to Figure 23, the "new" first image associated with the DAC's higher data rate after interpolation is "pushed" out further relative to the input signal. The "old" first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased thus reducing the complexity of the analog filter. The digital interpolation filters for I and Q paths are identical 43 tap halfband symmetric FIR filters. Each filter receives deinterleaved I or Q data from the digital input interface. The input CLOCK signal is internally divided by two to generate the filter clock. The filters are implemented with two parallel paths running at the filter clock rate. The output from each path is selected on opposite phases of the filter clock, thus producing interpolated filtered output data at the input clock rate. The frequency response and impulse response of these filters are shown in Figures 2a and 2b. Table I lists the idealized filter coefficients that correspond to the filter's impulse response. The digital section of the AD9761 also includes an input interface section designed to support interleaved I and Q input data from a single 10-bit bus. This section de-interleaves the I and Q input data while ensuring its proper pairing for the 2x interpolation filters. A SLEEP/RESET input serves a dual function by providing a reset function for this section as well as providing power down functionality. Refer to the DIGITAL INPUT AND INTERFACE CONSIDERATIONS and SLEEP/RESET sections for a more detailed discussion.
DAC TRANSFER FUNCTION
Note, the full-scale value of VIOUTA and VIOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VIDIFF, appearing across IOUTA and IOUTB is: VIDIFF =(IIOUTA - IIOUTB) x RLOAD (7) Substituting the values of IIOUTA, I IOUTB, and IREF; VIDIFF can be expressed as: VIDIFF ={(2 DAC CODE - 1023)/1024)} x (16 R LOAD/R SET) x VREFIO (8)
These last two equations highlight some of the advantages of operating the AD9761 differentially. First, differential operation will help cancel common-mode error sources associated with IIOUTA and IIOUTB such as noise and distortion. Second, the differential code dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (i.e., VIOUTA or VIOUTB) thus providing twice the signal power to the load.
REFERENCE OPERATION
Each I and Q DAC provides complementary current output pins: IOUT(A/B) and QOUT(A/B) respectively. Note, QOUTA and QOUTB operate identically to IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while IOUTB, the complementary output, provides no current. The current output of IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as: IIOUTA = (DAC CODE/1024) x IOUTFS IIOUTB = (1023 - DAC CODE)/1024 x IOUTFS where: DAC CODE = 0 to 1023 (i.e., Decimal Representation). As previously mentioned, IOUTFS is a function of the reference current, IREF, which is nominally set by a reference, VREFIO, and external resistor, RSET . It can be expressed as: IOUTFS = 16 x IREF where: IREF = VREFIO/R SET (3) (4) (1)
The AD9761 contains an internal 1.20 V bandgap reference which can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM as shown in Figure 24, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be filtered externally with a ceramic chip capacitor of 0.1 F or greater from REFIO to REFLO. Also, REFIO should be buffered with an external amplifier having a low input bias current (i.e., <1 A) if any additional loading is required.
0.1 F OPTIONAL EXTERNAL REF BUFFER FOR ADDITIONAL LOADS
REFLO +1.2V REF REFIO
COMP2 50pF
AVDD
0.1 F
(2)
COMPENSATION CAPACITOR REQUIRED
FSADJ
CURRENT SOURCE ARRAY
RSET 2k
AD9761
Figure 24. Internal Reference Configuration
The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The single-ended voltage output appearing at IOUTA and IOUTB pins is simply: VIOUTA = IIOUTA x R LOAD VIOUTB = IIOUTB x RLOAD REV. A (5) (6)
The internal reference can also be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 25. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is disabled and the high input impedance (i.e., 1 M) of REFIO minimizes any loading of the external reference.
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AD9761
AVDD 0.1 F
REFLO AVDD +1.2V REF EXT. VREF RSET IREF = VREF/RSET REFIO FSADJ
COMP2 50pF
AVDD
- +
CURRENT SOURCE ARRAY
AD9761
Depending on the requirements of the application, IREF can be adjusted by varying either RSET, or in the external reference mode, by varying the REFIO voltage. IREF can be varied for a fixed RSET by disabling the internal reference and varying the voltage of REFIO over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 M, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 26 using the AD7524 and an external 1.2 V reference, the AD1580.
ANALOG OUTPUTS
Figure 25. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9761 also contains an internal control amplifier which is used to simultaneously regulate both DAC's full-scale output current, IOUTFS. Since the I and Q IOUTFS are derived from the same voltage reference and control circuitry, excellent gain matching is ensured. The control amplifier is configured as a V-I converter as shown in Figure 25 such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation (4). IREF is copied over to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation (3). The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 1 mA to 10 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9761's analog supply, AVDD, which is proportional to IOUTFS (refer to the POWER DISSIPATION section). The second benefit relates to the 20 dB adjustment span which may be useful for system gain control purposes. Optimum noise and dynamic performance for the AD9761 is obtained with a 0.1 F external capacitor installed between COMP2 and AVDD. The bandwidth of the reference control amplifier is limited to approximately 5 kHz with a 0.1 F capacitor installed. Since the -3 dB bandwidth corresponds to the dominant pole and hence its dominant time constant, the settling time of the control amplifier to a stepped reference input response can be easily determined. Note, the output of the control amplifier, COMP2, is internally compensated via a 50 pF capacitor thus ensuring its stability if no external capacitor is added.
As previously stated, both the I and Q DACs produce two complementary current outputs which may be configured for single-end or differential operation. IIOUTA and IIOUTB can be converted into complementary single-ended voltage outputs, VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in the DAC TRANSFER SECTION by Equations 5 through 8. The differential voltage, VIDIFF, existing between VIOUTA and VIOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Figure 27 shows an equivalent circuit of the AD9761's I (or Q) DAC output. It consists of a parallel array of PMOS current sources in which each current source is switched to either IOUTA or IOUTB via a differential PMOS switch. As a result, the equivalent output impedance of IOUTA and IOUTB remains quite high (i.e., >100 k and 5 pF).
AD9761
AVDD
IOUTA RLOAD
IOUTB RLOAD
Figure 27. Equivalent Circuit of the AD9761 DAC Output
IOUTA and IOUTB have a negative and positive voltage compliance range which must be adhered to achieve optimum performance. The negative output compliance range of -1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage.
AVDD OPTIONAL BANDLIMITING CAPACITOR REFLO COMP2 50pF AVDD
AVDD
1.2V AD1580
OUT1
RFB
VDD 0.1V TO 1.2V
+1.2V REF REFIO FSADJ IREF = VREF/RSET
AD7524 OUT2 VREF AGND
- +
CURRENT SOURCE ARRAY
RSET DB7-DB0
AD9761
Figure 26. Single-Supply Gain Control Circuit
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REV. A
AD9761
The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 10 mA to 1.00 V for an IOUTFS = 2 mA. Applications requiring the AD9761's output (i.e., VOUTA and/or VOUTB) to extend to its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9761's linearity performance and subsequently degrade its distortion performance. Note, the optimum distortion performance of the AD9761 is obtained by restricting its output(s) as seen at IOUT(A/B) and QOUT(A/B) to within 0.5 V.
DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATIONS
while data is repeatedly writing to the AD9761, the data will be written into the selected filter register at half the input data rate since the data is always assumed to be interleaved. The state machine controls the generation of the divided clock and hence pairing of I and Q data inputs. After the AD9761 is reset, the state machine keeps track of the paired I and Q data. The state transition diagram is shown in Figure 29, in which all the states are defined. A transition in state occurs upon the rising edge of CLOCK and is a function of the current state as well as status of SELECT, WRITE and SLEEP. The state machine is reset on the first rising CLOCK edge while RESET remains high. Upon RESET returning low, a state transition will occur on the first rising edge of CLOCK. The most recent I and Q data samples are transferred to the correct interpolation filter only upon entering state FILTER DATA. Note, it is possible to ensure proper pairing of I and Q data inputs without issuing RESET high. This may be accomplished by writing two or more successive Q data inputs followed by a clock. In this case, the state machine will advance to either the RESET or FILTER DATA state. The state machine will advance to the ONE-I state upon writing I data followed by a clock.
I or Q or N ONE, I Q FILTER DATA N I Q or N RESET
The AD9761 digital interface consists of 10 data input pins, a clock input pin, and three control pins. It is designed to support a clock rate up to 40 MSPS. The 10-bit parallel data inputs follow standard positive binary coding, where DB9 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA (or QOUTA) produces a full-scale output current when all data bits are at Logic 1. IOUTB (or QOUTB) produces a complementary output, with the full-scale current split between the two outputs as a function of the input code.
"I" AND "Q" DATA
"I" INPUT REGISTER
"I" FILTER REGISTER
I
"I" DATA
"Q" INPUT REGISTER
"Q" INPUT REGISTER
"Q" DATA
I = WRITE & SELECT FOLLOWED BY A CLOCK Q = WRITE & SELECT FOLLOWED BY A CLOCK N = CLOCK ONLY, NO WRITE
CLOCK 2 CLOCK SELECT RESET/SLEEP WRITE STATE MACHINE
Figure 29. State Transition Diagram of AD9761 Digital Interface
Figure 28. Block Diagram of Digital Interface
The AD9761 interfaces with a single 10-bit digital input bus that supports interleaved I and Q input data. Figure 28 shows a simplified block diagram of the digital interface circuitry consisting of two banks of edge triggered registers, two multiplexers, and a state machine. Interleaved I and Q input data is presented at the DATA input bus, where it is then latched into the selected I or Q input register on the rising edge of the WRITE input. The output of these input registers is transferred in pairs to their respective interpolator filters' register after each Q write on the rising edge of the CLOCK input (refer to Timing Diagram in Figure 2). A state machine ensures the proper pairing of I and Q input data to the interpolation filter's inputs. The SELECT signal at the time of the rising edge of the WRITE signal determines which input register latches the input data. If SELECT is high around the rising edge of WRITE the data is latched into the I register of the AD9761. If SELECT is low around the rising edge of the WRITE, the data is latched into the Q register of the AD9761. If SELECT is kept in one state REV. A
An example helps illustrate the digital timing and control requirements to ensure proper pairing of I and Q data. In this example, the AD9761 is assumed to interface with a host processor on a dedicated data bus and the state machine is reset by asserting a Logic Level "1" to the RESET/SLEEP input for a duration of one clock cycle. In the timing diagram shown in Figure 30, WRITE and CLOCK are tied together while SELECT is updated at the same instance as DATA. Since SELECT is high upon RESET returning low, I data is latched into the I input register on the first rising WRITE. On the next rising WRITE edge, the Q data is latched into its input register and the outputs of both input registers are latched into their respective I and Q filter registers. The sequence of events is repeated on the next rising WRITE edge with the new I data being latched into the I input register. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 ( 20%). The internal digital circuitry of the AD9761 is capable of operating over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage, VOH(MAX), of the TTL drivers. A DVDD of 3 V to 3.3 V will typically
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AD9761
ensure proper compatibility of most TTL logic families. Figure 31 shows the equivalent digital input circuit for the data, sleep and clock inputs.
RESET
POWER DISSIPATION
DATA
I0
Q0
I1
Q1
SELECT
The power dissipation of the AD9761 is dependent on several factors which include: (1) AVDD and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK , the update rate; (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in Figure 32 and is insensitive to fCLOCK.
30
CLOCK/WRITE
Figure 30. Timing Diagram
DVDD IAVDD - mA DIGITAL INPUT
25
20
15
10
5
Figure 31. Equivalent Digital Input
0
1
2
3
4
Since the AD9761 is capable of being updated up to 40 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold-times of the AD9761 as well as its required min/max input logic level thresholds. The external clock driver circuitry should provide the AD9761 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that can manifest itself as phase noise on a reconstructed waveform. Digital signal paths should be kept short, and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 to 100 ) between the AD9761 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs, which contributes to data feedthrough. Operating the AD9761 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough.
RESET/SLEEP MODE OPERATION
5 6 IOUTFS - mA
7
8
9
10
Figure 32. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 33 and 34 show IDVDD as a function of a full-scale sine wave output ratio's (fOUT/ fCLOCK) for various update rate with DVDD = 5 V and DVDD = 3 V respectively.
70 60 50 IDVDD - mA 40 20 MSPS 30 2.5 MSPS 20 10 0 10 MSPS 5 MSPS 40 MSPS
The RESET/SLEEP input can be used either to power-down the AD9761 or reset its internal digital interface logic. If the RESET/ SLEEP input is asserted for greater than one clock cycle but under four clock cycles by applying a logic level "1," the internal state machine will be reset. If the RESET/SLEEP input is asserted for four clock cycles or longer, the power-down function of the AD9761 will be initiated. The power-down function turns off the output current and reduces the supply current to less than 9 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. The power-up and power-down characteristics of the AD9761 is dependent upon the value of the compensation capacitor connected to COMP1 and COMP3. With a nominal value of 0.1 F, the AD9761 takes less than 5 s to power down and approximately 3.25 ms to power back up.
0
0.05
0.1 RATIO - fOUT/fCLK
0.15
0.2
Figure 33. IDVDD vs. Ratio @ DVDD = 5 V
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REV. A
AD9761
40
AD9761
35 30 IDVDD - mA 25 20 20 MSPS 15 2.5 MSPS 10 5 0 10 MSPS 5 MSPS IOUTB 40 MSPS IOUTA
MINI-CIRCUITS T1-1T RLOAD
OPTIONAL RDIFF
Figure 35. Differential Output Using a Transformer
0
0.05
0.1 RATIO - fOUT/fCLK
0.15
0.2
Figure 34. IDVDD vs. Ratio @ DVDD = 3 V
APPLYING THE AD9761
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD9761. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 10 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
The center-tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9761. A differential resistor, RDIFF, may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable requiring double termination. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination which results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF .
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential to singleended conversion as shown in Figure 36. The AD9761 is configured with two equal load resistors, RLOAD, of 50 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp's input.
500 200 IOUTA AD8042 IOUTB COPT RLOAD 50 200 RLOAD 50
AD9761
An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 35. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers passband. An RF transformer such as the Mini Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only.
500
Figure 36. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8042 is configured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9761 while meeting other system level objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
REV. A
-15-
AD9761
The differential circuit shown in Figure 37 provides the necessary level-shifting required in a single supply system. In this case, AVDD, which is the positive analog supply for both the AD9761 and the op amp is also used to level-shift the differential output of the AD9761 to midsupply (i.e., AVDD/2).
AD9761 AD9761
IOUTA IOUTB COPT RLOAD 50 200 RLOAD 50 1k AVDD 1k 200 AD8042 500 IOUTA IOUTB 50 ** 50 ** AVDD QUADRATURE UPCONVERTER 500 * 500 * VIN+ VIN- 500 * 500 *
*OHMTEK TO MC-1603-5000D **OHMTEK TO MC-1603-1000D
Figure 39. Differential, DC Coupled Output Configuration with Level-Shifting Figure 37. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT POWER AND GROUNDING CONSIDERATIONS
Figure 38 shows the AD9761 configured to provide a unipolar output range of approximately 0 V to +0.5 V since the nominal full-scale current, IOUTFS, of 10 mA flows through an RLOAD of 50 . In the case of a doubly terminated low-pass filter, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to.
AD9761
IOUTA IOUTB 50
In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection; placement and routing; and supply bypassing and grounding. The evaluation board for the AD9761, which uses a four-layer PC board, serves as a good example for the above mentioned considerations. The evaluation board provides an illustration of the recommended printed circuit board ground, power and signal plane layout. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9761 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply should be decoupled as closely as physically as possible to DCOM. For those applications requiring a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 40. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors.
AVDD TTL/CMOS LOGIC CIRCUITS FERRITE BEADS + 100 F - ELECT. + 10-22 F - TANT. 0.1 F CER. ACOM
IOUTFS = 10mA
VOUT = 0V TO 0.5V 50
Figure 38. 0 V to +0.5 V Unbuffered Voltage Output
DIFFERENTIAL, DC COUPLED OUTPUT CONFIGURATION WITH LEVEL SHIFTING
Some applications may require the AD9761 differential outputs to interface to a single supply quadrature upconverter. Although most of these devices provide differential inputs, its commonmode voltage range does not typically extend to ground. As a result, the ground-referenced output signals shown in Figure 38 must be level shifted to within the specified common-mode range of the single-supply quadrature upconverter. Figure 39 shows the addition of a resistor pull-up network which provides the level shifting function. The use of matched resistor networks will maintain maximum gain matching and minimum offset performance between the I and Q channels. Note, the resistor pull-up network will introduce approximately 6 dB of signal attenuation.
+5V OR +3V POWER SUPPLY
Figure 40. Differential LC Filter for Single +5 V or +3 V Applications
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REV. A
AD9761
Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9761. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath, or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some "free" capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. Its is recommended that all connections be short, direct and as physically close to the package as possible, in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistor should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices' application notes AN-280 and AN-333.
APPLICATIONS Using the AD9761 for QAM Modulation
A common and traditional implementation of a QAM modulator is shown in Figure 41. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components, respectively. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shapes and limits each component's spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the QAM signal.
IOUT DSP OR ASIC 10
AD9761
QOUT
CARRIER FREQ
0 90
TO MIXER
NYQUIST FILTERS
QUADRATURE MODULATOR
Figure 41. Typical Analog QAM Architecture
EVALUATION BOARD
The AD9761-EB is an evaluation board for the AD9761 dual 10-bit, 40 MSPS DAC. Careful attention to layout and circuit design along with prototyping area, allows the user to easily and effectively evaluate the AD9761. This board allows the user the flexibility to operate each of the AD9761 DACs in a singleended or differential output configuration. Each of the DACs' single-ended outputs are terminated in a 50 resistor. Evaluation using a transformer coupled output can be accomplished simply by installing a Minicircuit transformer (i.e., Model T2-1T) into the available socket. The digital inputs are designed to be driven directly from various word generators with the onboard option to add a resistor network for proper load termination. Separate 50 terminated SMA connectors are also provided for the CLOCK, WRITE and SELECT inputs. Provisions are also made to operate the AD9761 with either the internal or an external reference as well as to exercise the power-down feature.
QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDM as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency that is modulated both in amplitude (i.e., AM modulation) and in phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency.
REV. A
-17-
AD9761
Figure 42a. Evaluation Board Schematic
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REV. A
AD9761
Figure 42b. Evaluation Board Schematic
REV. A
-19-
AD9761
Figure 43. Silkscreen Layer--Top
Figure 44. Component Side PCB Layout (Layer 1)
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REV. A
AD9761
Figure 45. Ground Plane PCB Layout (Layer 2)
Figure 46. Power Plane PCB Layout (Layer 3)
REV. A
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AD9761
Figure 47. Solder Side PCB Layout (Layer 4)
Figure 48. Silkscreen Layer--Bottom
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REV. A
AD9761
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
8 0.015 (0.38) SEATING 0.009 (0.229) 0 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
REV. A
-23-
PRINTED IN U.S.A.
C3150-0-2/00 (rev. A)

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